1. Field of the Invention
This invention is directed to the testing of logic array devices. It concerns, more particularly, error detection and correction apparatus for a logic array which consists of an AND array and an OR array.
2. Description of the Prior Art
Logic array devices of many kinds are well known. If any such device is programmable, it is commonly referred to as a "programmable logic array" or PLA as identified hereinafter. In a typical operation, signals corresponding to a number of binary variables are applied to the input of a PLA and, in accordance with the logic wiring and/or the programmed generation of conductive crosspoints, output signals are obtained on particular function or output lines. PLAs are preferably used as function controls in data processing systems. For this purpose, the binary operation signals of an instruction are applied to the PLA input and the data flow is controlled by means of output signals on particular function lines.
With very few exceptions, known PLAs have the disadvantage that, during their operation in a data processing system, they cannot be tested to insure that they are operating properly. Consequently, to date, PLAs have been tested either prior to their installation in a system or by applying particular test signals and comparing the resultant output signals with known ideal values. Alternatively, one can also interrupt normal system operation and, using special purpose test patterns and diagnostic routines, ascertain the operating soundness of a particular PLA while it is in place.
One prior art approach to this problem is described in U.S. Pat. No. 3,958,110 to Hong et al. In this particular arrangement, logic performing arrays are fabricated to include testing circuitry therewithin. This PLA internal test circuitry eliminates the need for storing information as to the logic functions performed by any particular array and further permits the employment of a uniform testing sequence callable to test all arrays used. Also of possible interest is U.S. Pat. No. 4,140,967 to Balasubramanian et al which describes a testing technique and special testing circuitry for a particular PLA. This technique makes use of the existing bit partitioning input buffer as the source of test patterns and the existing output latches as the storage means for the test response bits of the individually tested components in a merged PLA.
In one special case, a PLA could also be tested using a distinctive personalization as is described in the IBM Technical Disclosure Bulletin, Vol. 18, No. 7, December 1975, at pages 2044 to 2046 thereof. Another special case approach of testing a PLA by checking appropriate voltage values, at the PLA's site and during its operation, is detailed in the IBM Technical Disclosure Bulletin, Vol. 19, No. 2, July 1978, at pages 588 to 590. A final example of the special case approach is described in the IBM Technical Disclosure Bulletin, Vol. 21, No. 5, October 1978, at page 2008. In this arrangement, a PLA is tested by adding special input lines and then utilizing parity signals to verify error-free performance.
All of the foregoing prior art arrangements have the disadvantage that systemic and complete in-situ testing of the logic array, if at all possible, is extremely time consuming. A complete test of the logic array with the aid of test signals requires a great number of signal thruput combinations thereby adding a significant time penalty to the testing procedure. The special cases of testing an installed PLA during its operation, as described above, have the disadvantage that either alternative applications are not tested or that the logic array is only suitable for the actual combinations of input signals applied to the PLA in the test. In addition, such arrangements have the further disadvantage that errors, when they occur, cannot be corrected and the entire system must be shut down.